1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) type of semiconductor memory device, and more particularly to a reliable self-refreshing operation of a DRAM type of semiconductor memory device.
2. Description of Related Art
In a conventional DRAM type of semiconductor memory device, a data stored in a memory cell disappears because of discharge if a refresh operation is not executed for a long time. Therefore, it is necessary to execute a self-refreshing operation periodically before the stored data disappears. Typically, the DRAM type of semiconductor memory device enters the self-refreshing mode when a control signal satisfies a predetermined condition and automatically executes a self-refreshing operation. In this case, an internal row address signal and a timing signal for it are generated and the self-refreshing operation is continued while power is supplied to the semiconductor memory device.
FIG. 1 is a block diagram of a conventional self-refreshing circuit of a DRAM type of semiconductor memory device. Referring to FIG. 1, the conventional self-refreshing circuit includes a timer circuit 101x for generating a timer signal .phi.t from an oscillation signal internally generated in response to a self-refresh entry signal SRE inputted thereto, an oscillation frequency switching circuit 105 for switching the period of the timer signal .phi.t, a self-refresh control circuit 102, a RAS control circuit 103 and an internal row address counter 104 connected to a memory cell array (not shown) including a plurality of memory cells arranged in column and row directions in a matrix manner. The timer circuit 101x includes a ring oscillator 111 oscillating in response to the self-refresh entry signal SRE to generate an internal reference clock signal ICK having a predetermined period of time, and a counter circuit 112 for counting or dividing the clock signal ICK to generate the timer signal .phi.t having a predetermined period of time. The oscillation frequency switching circuit 105 allows the frequency of clock signal ICK to be switched such that the clock signal ICK has a longer time period. The self-refresh control circuit 102 generates the self-refresh entry signal SRE in a high level in response to a self-refresh mode detecting signal SRED which becomes active when a predetermined self-refresh condition is satisfied, and generates an internal RAS signal RASI which becomes active (the high level) in synchronous with the timer signal .phi.t and becomes inactive in response to a refresh end signal RFE inputted thereto. The RAS control circuit 103 includes logic gates G104 and G105 and control signal generating circuit 131. The RAS control circuit 103 generates and outputs the refresh end signal RFE to the self-refresh control circuit 102 and a signal CC to the internal row address counter 104. More particularly, while the self-refresh entry signal SRE is active, a RAS signal RAS is generated in response to the falling down of an external RAS signal RASE in synchronous with the timer signal .phi.t by the logic gates G104 and G105 and then in response to the RAS signal RAS by the control signal generating circuit 131 a counter control signal CC is generated in synchronous with the rising of the RAS signal RAS and the refresh end signal RFE is generated after a predetermined time interval from when the counter control signal CC is generated. The internal row address counter 104 generates an internal row address signal CX (CXO, CX1, . . . , CXn) sequentially updated in synchronous with the counter control signal CC. Data stored in the plurality memory cells of the memory cell array is sequentially refreshed in accordance with the internal row address signal CX.
Next, the refresh operation of the conventional DRAM type of semiconductor device will be described below with reference to FIGS. 2A to 2G.
First, when it is informed by a control signal that a condition for the self-refresh mode is satisfied, the self-refresh mode detection signal SRED is made active. The self-refresh control circuit 102 sets the self-refresh entry signal SRE in an active state (a high level) in response to the transition of the self-refresh mode detection signal SRED to the active state to enter the self-refresh mode, as shown in FIG. 2A.
In response to the active self-refresh entry signal SRE, the ring oscillator 111 starts oscillation to generate the oscillation signal as an internal reference clock signal ICK having a predetermined time period and supplies the signal ICK to the counter circuit 112. The counter circuit 112 counts or divides the internal reference clock signal ICK in such a manner that the timer signal .phi.t is generated to have a period of time integral times longer than that of the signal ICK, as shown in FIG. 2B. The timer signal .phi.t is supplied to the self-refresh control circuit 102.
The self-refresh control circuit 102 makes the internal RAS signal RASI active in synchronous with the timer signal .phi.t, as shown in FIG. 2C and the signal RASI is supplied to the RAS control circuit 103. At this time, in the RAS control circuit 3, since the self-refresh entry signal SRE is in the active level, the internal RAS signal RASI is passed through to the RAS control signal generating circuit 131 as the RAS signal RAS when the external RAS signal RASE is made active (a low level), as shown in FIG. 2D. The generating circuit 131 generates the counter control signal CC in synchronous with the rising of the RAS signal RAS as shown in FIG. 2F and the signal CC is supplied to the internal row address counter 104. The internal row address counter 104 generates the internal row address signal CX in response to the counter control signal CC to update the row address as shown in FIG. 2G. As a result, the refresh operation is performed to the row of the memory cell array having the row address outputted from the internal row address counter 104. At the timing when the refresh operation to the row is completed, the RAS control signal generating circuit 131 generates the refresh end signal RFE and supplies to the self-refresh control circuit 102 as shown in FIG. 2E. The self-refresh control circuit 102 makes the internal RAS signal RASI inactive in response to the refresh end signal RFE.
Thereafter, the next timer signal .phi.t is inputted to the self-refresh control circuit 102 and the above-mentioned operation is repeated. In this manner, the memory cell array can be refreshed in units of rows by repeatedly supplying the timer signal .phi.t.
On the other hand, since data holding time of each of the memory cells of the memory cell array changes greatly depending upon the ambient temperature, the ambient temperature change greatly affects the period of time of the refresh operation. FIG. 3 shows a relation of the data holding time and the temperature. In FIG. 3, the ordinate indicates a logarithmic data holding time and the abscissa indicates the ambient temperature. As seen from the figure, the logarithmic data holding time is linearly and reversely proportional to the ambient temperature. Since a usable temperature region is regulated in a region of temperature T.sub.L to temperature T.sub.H in the semiconductor memory device such as a dynamic RAM, the period of the timer signal .phi.t (to be referred to as a timer period hereinafter) is set in such a manner that the refresh operation can be normally performed in the usable temperature region. More particularly, since the allowable timer period is tab at the maximum usable temperature where the data holding time is the shortest, the timer period .phi.t needs to be set to tab or shorter. Further, since the data holding time has one of dispersed values, the timer period .phi.t needs to be set to t.sub.dh or shorter, taking the worst case into account. Even if a manufacturer intends to guarantee the self-refresh operation, since the timer period .phi.t does not almost have the temperature dependency, the wafer test process at the room temperature T.sub.A cannot guarantee the self-refresh operation at the maximum usable temperature T.sub.H. Therefore, the data holding time t.sub.da at the room temperature T.sub.A is guaranteed in correspondence to the data holding time t.sub.dh at the maximum usable temperature T.sub.H.
With the consumed current, current in the self-refresh operation (IccSR) is reversely proportional to the timer period, i.e. , refresh period. That is, the longer timer period is advantageous from the viewpoint of the consumed current. On the contrary, the longer timer period is severe in the data holding time and has the possibility of data holding fault. For this reason, recently, the products of semiconductor memory device is classified depending upon the timer period. That is, a semiconductor memory device having a longer data holding time is used in a longer timer period and a semiconductor memory device having a shorter data holding time used in a shorter timer period.